Cadence SPB OrCAD 16.5.023 (Allegro SPB) Hotfix



Cadence SPB OrCAD 16.5.023 (Allegro SPB) Hotfix | 655.7 Mb

Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.



To stay competitive in today's market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, Cadence OrCAD personal productivity tools have a long history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to boost productivity and accelerate time to market.

DATE: 05-30-2012 HOTFIX VERSION: 023
CCRID PRODUCT PRODUCTLEVEL2 TITLE
995566 ALLEGRO_EDITOR REPORTS Drill data file qty not matching drill chart
999003 LAYOUT TRANSLATORS L2A leaves unconnected nets and improper voids on vias
1008451 LAYOUT TRANSLATORS The brd file translated using L2A Translator is loosing the diameter of the copper area attached to the pin.
1010374 LAYOUT TRANSLATORS Layout MAX file is not getting converted to OrCAD Peformance correctly
1012375 ALLEGRO_EDITOR PARTITION Route Keepout in All subclass shape in .dpf cannot be imported back to master board.
1012522 ALLEGRO_EDITOR OTHER Allegro crashes during Import > Logic > Deisgn HDL and creates a .SAV file.
1012765 ALLEGRO_EDITOR EDIT_ETCH Allegro crash
1012934 CONCEPT_HDL CONSTRAINT_MGR Backannotation destroys matchgroups in replicated blocks in customer design
1012951 CONCEPT_HDL CORE Text justification corrupted on symbol mirror
1013030 SIG_INTEGRITY SIGNOISE PCB SI crashes when running bus simulations
1013519 APD GRAPHICS The layer selection in the Visibility Form slows down after selecting "Nets" in the Color Dialog.
1013853 CONSTRAINT_MGR OTHER Override constraints not working
1013942 APD COLOR Assign color is inconsistently assigning colors to the clines but not the vias.
1014402 CONCEPT_HDL CORE DE HDL crashes while saving some pages
1014757 SIG_INTEGRITY GEOMETRY_EXTRACT Huge Difference in Differential Impedance values in Cross Section between Bem2d and Ems2d Field Solver.
1014956 SIP_LAYOUT DIE_EDITOR die editor pin move and add commands put things on the half grid and not on the grid as expected

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

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